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| VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 Features * 34 Input by 34 Output Crosspoint Switch * 2.5 Gbits/sec. NRZ Data Bandwidth * TTL Compatible P Interface * Differential PECL Data Inputs * On-chip 50 Input Terminations 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection * 50 Source Terminated PECL Output Drivers * Single 3.3V Supply * 14W Maximum Power Dissipation * High Performance 256 BGA Package General Description The VSC835 is a monolithic 34x34 asynchronous crosspoint switch, designed to carry broadband data streams at up to 2.5 Gbit/s. The non-blocking switch core is programmed through a parallel port interface that allows random access programming of each output port. A high degree of signal integrity is maintained through the chip through fully differential signal paths. The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 34:1 multiplexer tree that can be programmed to one and only one of its 34 inputs, and each data input can be routed to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The signal path is asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each input channel and each output channel has an signal monitor function that can be used to identify loss of activity (LOA). An interrupt pin is provided to signal LOA, after which an external controller can query the chip to determine the channel(s) on which the fault occurred. Each output driver is a fully differential switched current driver with on-die back-terminations for maximum signal integrity. Data inputs are terminated on die through 50 ohm resistors terminated to VTERM. The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible with a microprocessor-style interface. The control port provides access to all chip functions, including LOA and programming. Program buffering is provided to allow multiple program assignments to be queued and issued simultaneously via a single configure command. VSC835 Block Diagram A0 Y0 A33 Control Logic P interface Y33 G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Figure 1: Detailed Block Diagram Datasheet VSC835 A,AN[33:0] 34 x 34 switch core LOA monitor 34 output drivers Y,YN[33:0] Program memory Control interface DATA[5:0], ADDR[5:0] ALE, CSB, WRB, RDB INTB, MONCLK, CONFIG Functional Description Data Paths All input data must be differential and biased to PECL levels. On-chip terminations are provided, with a nominal impedance of 50 ohms. All input termination resistors are tied to VTERM. Data outputs are provided through differential current switches with on-chip terminations that produce a PECL level output swing. The drive level of the output circuit is designed to produce standard PECL levels when terminated in 50 ohms to 2.0 volts. Other termination voltages are possible, such as to VCC or 1.3 volts, but the voltage level of the output will be shifted from its nominal value. The common-mode voltage of the output swing can be adjusted using the VCOM pins. The adjustment range is not calibrated, but typically allows for +/- 200mV of adjustment in common-mode voltage. The VCOM pin self-biases to a nominal value when left unconnected. Output channels can be powered off in pairs if fewer than 34 outputs are required. By connecting the VEE pin associated with a given pair of outputs to VCC, the output pairs will pull to VCC and chip power will be reduced by approximately 300mW per pair. Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Programming Interface The switch core is programmed through a parallel interface circuit that allows random reads or writes to the program memory array. The program memory array is buffered to allow multiple programming instructions to be loaded simultaneously with the CONFIG pin. Parallel programing can be clocked at up to a 50MHz rate and state read-back can be performed at up to 25MHz. The program data is composed of two parts: output address and input address. The output address, denoted by ADDR[5:0], specifies which output channel is to be programmed. The input address, denoted by DATA[5:0], specifies which input port the switch slice should connect to. The format of the program data is simple binary. For example: ADDR[5:0] (000100) / DATA[5:0] (000110) would direct output channel Y4 to connect to input channel A6. The programming state may be verified (read back) by applying the address of the desired output and asserting RDB. The programming state is unknown at power-on. Additional address space is provided for access to the monitor registers (see sections below). The microprocessor interface consists of the following signals. Levels are TTL (see DC Characteristics) : Table 1: Programming Interface Signal Table Pin D[5:0] A[5:0] ALE CSB WRB RDB INTB I/O B I I I I I O Description Bidirectional data bus to transfer data to/from internal program registers Address bus to select internal program registers for read-write operations ALE functionality is not implemented at this time. Tie this pin High. Chip Select (Active Low): assert this pin whenever the part is being read or programmed. Write (Active Low): program data will be transferred to the first level internal registers on the rising edge of this signal (when CSB is also low). Read (Active Low): program data from the internal program or monitor registers will be read out on the data bus when this signal goes low (with CSB also low). Interrupt (Active Low): this signal is asserted when an LOA condition is found Configure (Active High): assert this signal to transfer queued program information from the first-level internal registers to the second-level registers, making the programming take effect. This signal may be tied high to leave the second-level registers transparent so all programming will take effect immediately. CSB must be active (low) when CONFIG is asserted. CONFIG may be tied to a highorder bit of the address bus Monitor states are transferred to monitor registers on the rising edge of this signal. MONCLK is not expected to exceed 3MHz. CONFIG I MONCLK I Loss of Activity (LOA) Monitoring The LOA function consists of an activity monitor on each input channel, connected directly to the pads. The state of a monitor (whether or not it has been toggled by an input transition) can be observed by applying the address1 of the monitor register corresponding to the signal of interest and asserting RDB. Each monitor register is four bits in length, covering the state of four inputs. There is one extra two-bit monitor for the 33rd and 34th inputs. The state of each monitor is transferred to the register on the rising edge of MONCLK, whereupon the activity monitor is cleared until more activity is detected. 1. See Memory Map Table G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 If any change in a monitor state occurs after sampling by MONCLK, an interrupt will be signalled by asserting INTB, and the user must identify the offending channel by reading the monitor states. The interrupt will be cleared when the corresponding activity monitor is read, but the monitor state will not be changed. If multiple monitors have triggered the interrupt, it will persist until all the corresponding monitors have been read. LOA requires a minimum signal level of 30-150mV peak-peak to recognize an input as active. This is required to distinguish noise on an unconnected signal (where both inputs float to the termination voltage) from activity on a live signal. A minimum of two transitions defines activity. The threshold signal level is controlled by the voltage on the VHYS pin. In order to keep the hysteresis in a useful range, it is recommended that VHYS be nominally tied to VCC (useful range is 2.0V to VCC ). . Table 2: Memory Map Address 00h 01h ... 21h 22h, 23h 24h, 25h 26h, 27h 28h, 29h 2Ah Access R/W R/W ... R/W R/O R/O R/O R/O R/O Description Output Y0's programmed input channel (write and then assert CONFIG to program) Output Y1's programmed input channel ... Output Y33's programmed input channel Rx Signal monitor for inputs [A0-A3], [A4-A7] (Logic `1'=No activity) Rx Signal monitor for inputs [A8-A11], [A12-A15] Rx Signal monitor for inputs [A16-A19], [A20-A23] Rx Signal monitor for inputs [A24-A27], [A28-A31] Rx Signal monitor for inputs [A32-A33] AC Characteristics Table 3: Data Path Parameter FRATE TISKW TOSKW tR, tF tR, tF tjP Data rate Input channel delay skew (1) Output channel delay skew (2) High-speed input rise/fall times, 20% to 80% (3) High-speed output rise/fall times, 20% to 80% Output data eye jitter, peak-peak, 231 PRBS (4) Description Min - Typ 300 300 - Max 2.5 150 150 100 Units Gbits/s ps ps ps ps ps note: Unless otherwise stated, all specifications are guaranteed but not tested. note 1: Skew between any two input channels to a given output. note 2: Skew between any two output channels from the same input channel. note 3: Required for high-speed output rise/fall spec at FRATE=2.5 Gbits/s. For lower rate signals, use 0.375/FRATE note 4: Broadband jitter added to a jitter-free signal; jitter is primarily in the form of ISI for random data Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 MONCLK Monitor State Monitor State Reg 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Figure 2: Figure 2: Interrupt Timing (Change in Monitor State Registers) INTB Figure 3: Figure 3: Interrupt Timing (No change in Monitor State Registers) MONCLK Monitor State Monitor State Reg INTB Figure 4: Figure 4: Program Timing ADR[5:0] D[5:0] CSB WRB RDB CONFIG TsCSB TsWRB ThWRB TsCONFIG G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 Table 4: Programming Port Interface Timing Parameter Tconfig TpdADDR TpdRDB Tpdint Tpdstate TsRDB ThRDB TsWRB ThWRB TsCONFIG TsCSB TpwCONFIG TpwWRB TpwRDB TtsDATA Switch configuration delay Data read propagation delay from ADDR Data read propagation delay from RDB (1) Interrupt propagation delay from MONCLK (2) MONCLK to internal state register change delay (2) ADDR to RDB setup time RDB to ADDR hold time WRB setup time (for either ADDR or DATA) WRB hold time (for either ADDR or DATA) WRB to CONFIG setup time CSB setup time (to either WRB or RDB) CONFIG pulse width (high) WRB pulse width (low and high) RDB pulse width (low and high) DATA tri-state delay (from either RDB or CSB) (2) Description Min 5 3 5 3 1 0 10 10 10 - Max 6 30 7 50 6 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 1: measured from falling edge. note 2: measured from rising edge. DC Characteristics (over the specified operating conditions) Table 5: Power Parameter ICC PT ITERM-V ITERM-E VCC supply current Total chip power VTERM supply current with VTERM =VCC-1.3V VTERM supply current with VTERM =VCC-2.0V Description (Max) 4060 14 ~0 -950 Units mA W mA mA Note: Icc Specified with outputs terminated with 50 ohms to +2.0V and Chip Vterm=+2.0V, Vcc = 3.45V Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 Table 6: Control Port input levels (TTL) Parameter VIH VIL IIH IIL VOH VOL IOZ 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Description Input HIGH voltage (TTL) Input LOW voltage (TTL) Input HIGH current (TTL) Input LOW current (TTL) Output HIGH voltage (TTL) Output LOW voltage (TTL) Tri-state output current (TTL) Min 2.0 0 -- -- 2.4 0.1 -100 Typ -- -- -- -- -- -- -- Max 3.5 0.8 500 -500 3.0 0.4 100 Units V V A A V V A Conditions -- -- VIN = 2.4V VIN = 0.5V IOH = 2mA IOL = 1.5mA VOUT = 0.4V-2.4V Table 7: Data input levels (differential PECL) Parameter VID VICM Description Input differential voltage Input common-mode voltage Min 400 1.8 Typ -- -- Max 1000 2.2 Units mV V Conditions -- VCC=3.3V Table 8: Data output levels (differential PECL) Parameter VOD VOCM Description Output differential voltage Output common-mode voltage Min 600 1.8 Typ -- -- Max 1000 2.2 Units mV V Conditions note 1 note 1 note 1: Nominal PECL mode, VCC=VCCP=3.3V, VEE=0, terminated 50ohms to +2.0V G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 Absolute Maximum Ratings Power Supply Voltage (VCC) Potential to GND ............................................................................-0.5 V to +4.0 V TTL Input Voltage Applied ................................................................................................... -0.5 V to Vcc+0.5 V ECL Input Voltage Applied .................................................................................................. -0.5 V to VCC +0.5 V Output Current (IOUT) ................................................................................................................................... 50 mA Input Current (IIN) ...................................................................................................................................... 50 mA VTERM Current (ITERM) ............................................................................................................................ 800 mA Case Temperature Under Bias (TC) ................................................................................................-55o to + 125oC Storage Temperature (TSTG) ...........................................................................................................-65o to + 150oC Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Operating Conditions Supply voltage (VEE) ......................................................................................................................................... 0 V Supply voltage (VCC) .............................................................................................................................+3.3V 5% Supply voltage (VCCP) ...........................................................................................................................+3.3V 5% Termination voltage (VTERM)...................................................................................................................VCC-1.3V Case Temperature Operating Range (T)................................................................................................ 0o to 85oC ESD Ratings Proper ESD procedures should be used when handling this product. The VSC835 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above TBD. Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Figure 5: I/O Equivalent Circuits 50 PAD 50 Vterm PECL Input Equivalent Circuit 15 50 PAD PAD isig isig PECL Output Equivalent Circuit VCC 1300 PAD 2000 VEE VCOM (L or R) Input Equivalent Circuit VCC PAD 2500 5000 5000 VEE VHYS Input Equivalent Circuit G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 Package Pin Descriptions The VSC835 is packaged in a 27x27mm 256 pin ball grid array package. The 256 BGA package is thermally enhanced and carries the high-speed signals over controlled impedance lines from the solder ball to the circuit die. The following sections describe the pinout and mechanical details of the VSC835. Figure 6: Functional Pinout Floorplan A0 A2 A4 A32 I/P LOS and termination 34:1 Switch slice Y1 34:1 Switch slice 34:1 Switch slice Y3 34:1 Switch slice Y2 Y0 Y31 34:1 Switch slice 34:1 Switch slice Y32 Y33 34:1 Switch slice I/P LOS and termination control logic A1 A3 A5 Programming interface A33 Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Figure 7: Pinout Diagram BALL GRID INDEX A B ADR1 ADR3 VCOMR C 20 19 18 17 16 15 14 13 12 11 ADR5 10 ALE 9 8 7 6 5 4 3 2 1 A2 A8 A14 ADR2 MONCLK A20 A26 A32 A0 A4 A6 A10 A12 ADR0 ADR4 A16 A18 A22 A24 A28 A30 D Y0 Y2 Y4 Y6 Y8 Y10 Y12 Y14 Y16 Y18 Y20 Y22 Y24 Y26 Y28 Y30 Y32 VCOML VHYS Y1 Y3 Y5 E F G VCC VEE VTERM Y7 Y9 Y11 Y13 Y15 Y17 Y19 H J K L BOTTOM VIEW Y21 Y23 Y25 Y27 Y29 Y31 Y33 T P R M N D5 A1 A5 A7 A11 A13 D4 D1 D2 D3 D0 WRB U CSB A17 A21 A23 A27 A29 A33 V RDB CONFIG W INTB A3 A9 A15 A19 A25 A31 Y G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Table 9: Package Pin Identification Signal Name A0, NA0 A1, NA1 A2, NA2 A3, NA3 A4, NA4 A5, NA5 A6, NA6 A7, NA7 A8, NA8 A9, NA9 A10, NA10 A11, NA11 A12, NA12 A13, NA13 A14, NA14 A15, NA15 A16, NA16 A17,NA17 A18, NA18 A19, NA19 A20, NA20 A21, NA21 A22, NA22 A23, NA23 A24, NA24 A25, NA25 A26, NA26 A27, NA27 A28, NA28 A29, NA29 A30, NA30 A31, NA31 A32, NA32 A33, NA33 C17, D17 V17, U17 A17, A16 Y17, Y16 D16, C16 U16, V16 C15, D15 V15, U15 A15, A14 Y15, Y14 D14, C14 U14, V14 C13, D13 V13, U13 A13, A12 Y13, Y12 D10, C10 V9, U9 C9, D9 Y9, Y8 A9, A8 U8, V8 D8, C8 V7, U7 C7, D7 Y7, Y6 A7, A6 U6, V6 D6, C6 V5, U5 C5, D5 Y5, Y4 A5, A4 U4, V4 Datasheet VSC835 Function Level PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL Pin High Speed Data Inputs Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Data Input Page 12 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 Table 9: Package Pin Identification Signal Name Y0, YN0 Y1, YN1 Y2, YN2 Y3, YN3 Y4, YN4 Y5, YN5 Y6, YN6 Y7, YN7 Y8, YN8 Y9, YN9 Y10, YN10 Y11, YN11 Y12, YN12 Y13, YN13 Y14, YN14 Y15, YN15 Y16, YN16 Y17, YN17 Y18, YN18 Y19, YN19 Y20, YN20 Y21, YN21 Y22, YN22 Y23, YN23 Y24, YN24 Y25, YN25 Y26, YN26 Y27, YN27 Y28, YN28 Y29, YN29 Y30, YN30 Y31, YN31 Y32, YN32 Y33, YN33 E18, E17 E3, E4 E20, F20 E1, F1 F17, F18 F4, F3 G18, G17 G3, G4 G20, H20 G1, H1 H17, H18 H4, H3 J18, J17 J3, J4 J20, K20 J1, K1 K17, K18 K4, K3 L18, L17 L3, L4 L20, M20 L1, M1 M17, M18 M4, M3 N18, N17 N3, N4 N20, P20 N1, P1 P17, P18 P4, P3 R18, R17 R3, R4 R20, T20 R1, T1 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Pin High Speed Data Outputs Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Function Level PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL PECL G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Table 9: Package Pin Identification Signal Name ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 D0 D1 D2 D3 D4 D5 ALE INTB RDB WRB CONFIG CSB MONCLK D12 C12 B11 C11 D11 A11 Y11 U11 V11 W11 V12 U12 A10 Y10 W10 U10 W9 V10 B10 A1, A2, A3, A18, A19, A20, B1, B2, B3, B18, B19, B20, C1, C2, C3, C18, C19, C20, D1, D2, D3, D18, D19, D20, U1, U2, U3, U18, U19,U20, V1, V2,V3,V18, V19, V20, W1, W2, W3, W18, W19, W20, Y1, Y2, Y3, Y18, Y19, Y20 B4, B6, B8, B9, B13, B14, B16, B17, D4, E2, E19, H2, H19, M2, M19, T3, T4, W5, W7, W8, W13, W14, W16, W17 F19 G19 J19 K19 L19 Datasheet VSC835 Function Level TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Pin Programming Port Program data address Program data address Program data address Program data address Program data address Program data address Program data Program data Program data Program data Program data Program data Address latch enable (active high) Interrupt (active low) Read enable (active low) Write enable (active low) Configuration strobe (active high) Chip select (active low) Loss of activity monitor clock (active high) Power Supplies VCC Power +3.3V VEE VEE VEE VEE VEE VEE Power GND Power for Output Channels 0,2 Power for Output Channels 4,6 Power for Output Channels 8,10 Power for Output Channels 12,14 Power for Output Channels 16,18 GND GND GND GND GND Page 14 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 Table 9: Package Pin Identification Signal Name VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VEE VTERM N19 P19 R19 T19 F2 G2 J2 K2 L2 N2 P2 R2 T2 B5, B7, B12, B15, W4, W6, W12, W15 T18 C4 T17 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Pin Function Power for Output Channels 20,22 Power for Output Channels 24,26 Power for Output Channels 28,30 Power for Output Channel 32 Power for Output Channels 1,3 Power for Output Channels 5,7 Power for Output Channels 9,11 Power for Output Channels 13,15 Power for Output Channels 17,19 Power for Output Channels 21,23 Power for Output Channels 25,27 Power for Output Channels 29,31 Power for Output Channel 33 Termination power Level GND GND GND GND GND GND GND GND GND GND GND GND GND +2.0V Misc. VCOML VCOMR VHYS Slicing level for Y0 - YN16 (even) Slicing level for Y1 - YN15 (odd) Loss of activity hysteresis threshold ANALOG ANALOG ANALOG G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 Package Information 27mm 256 BGA Package Drawing BOTTOM VIEW 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 A C E G H J K L M N P R T U V W Y B D F g DETAIL B g b 4 0.10 D -A-B- DETAIL B 11 A1 c TOP VIEW E (4 PLCS) DIMENSIONAL REFERENCES NOM. MAX. REF. MIN. 1.65 1.80 A 1.95 0.70 0.65 A1 0.60 26.80 27.00 27.20 D 24.13 (BSC.) D1 26.80 27.00 27.20 E 24.13 (BSC.) E1 0.65 0.75 0.85 b c 1.15 1.25 1.05 20 M 256 N aaa 0.25 ccc 0.25 e 1.27 TYP. 0.15 P g 0.40 0.50 F NOTES: Page 16 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC835 Ordering Information 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection The order number for this product is formed by a combination of the device number, and package type. VSC835 Device Type VSC835: 2.5 GHz 34x34 Crosspoint Switch with Signal Monitoring UB Package Style UB: 256 pin BGA package Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to placing orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52270-0, Rev. 4.1 7/24/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION 2.5 Gbits/sec 34x34 Crosspoint Switch with Signal Detection Datasheet VSC835 Page 18 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52270-0, Rev. 4.1 7/24/00 |
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